Went through the projects of "nand2tetris part 1" in a few hours over last evening and this. Very cute to cobble together a little cpu from nand gates. I guess I never appreciated the various relationships between other architectural choices and the choice of having a control FSM in a cpu versus not --- notably the nand2tetris cpu is single-cycle, and gets away with it because it's Harvard architecture (program lives in a different memory from data) so it can simultaneously read from program memory and data memory in a single cycle without any problem. The j1 gets away with being single cycle despite being von-Neumann by simply demanding a two-read-port RAM. So then under most other circumstances, you probably want multiple cycles to execute instructions; maybe you want cycle times to be as short as possible by chopping things up into pipeline stages, maybe you just want to squeeze instruction fetch and memory reads into the same RAM port.
Dunno, I bet all of this stuff is college-freshman-obvious to ECE folks, but it's neat to see it with fresh eyes coming from much higher up the abstraction ladder.