Check it out: Firrtl is a low-level-ish intermediate language that compiles to Verilog, that can be specified in like 50 pages of reasonably readable spec. More to the point, they describe it as a series of increasingly-low-level intermediate languages --- but all you have to do to get one from the next is just forbid one feature after another. And then Chisel is a scala DSL that compiles to Firrtl; so if you want a legit programming language with a modern (if a bit maddeningly everything-but-the-kitchen-sink) type system in which to express the computation of the circuit you're interested in, there you go. You need a tutorial? Got one. You need an entire open-source RISC-V processor implementation? Bam.
Best as I can understand it, Verilog corresponds mushily to both these levels of abstraction at the same time in confusing ways, and that's why it scares the heebie-jeebies out of PL nerds like me.